A gate matrix layout synthesis tool which utilizes folding technique on both rows and columns has been developed. The conventional interval graph model and the recently proposed dynamic net-list representation cannot fully depict circuit schematics, such as internet connections. The authors propose a novel graph-based model called hierarchical dynamic net-list to improve the schematic representation. They demonstrate this representation's advantages, such as pseudogates and internet connections, for plane partitioning and gate ordering phases. Five heuristic measurements in simulated annealing for plane partitioning were examined to find a good partition in the solution space. On the basis of the proposed model, the folded layout area in the partitioning phase can be more accurately estimated. The new gate ordering algorithm also utilizes the advantages of the hierarchical dynamic net-list model to handle the gate placement in the folded layouts. The experimental results show 12% to 15% improvement in layout area for small circuits and 30% improvement for a large circuit.