Gate oxide leakage and delay tradeoffs for dual-Tox circuits

Anup K. Sultania, Dennis Sylvester, Sachin S. Sapatnekar

Research output: Contribution to journalArticlepeer-review

7 Scopus citations


Gate oxide tunneling current (Igate) is comparable to subthreshold leakage current in CMOS circuits when the equivalent physical oxide thickness (Tox) is below 15 ̊. Increasing the value of T ox reduces the leakage at the expense of increased delay, and hence a practical tradeoff between delay and leakage can be achieved by assigning one of two permissible Tox values to each transistor. In this paper, we propose an algorithm for dual-Tox assignment to optimize the total leakage power under delay constraints and generate a leakage/delay tradeoff curve. As compared to the case where all transistors are set to low T ox, our approach achieves an average leakage reduction of 86% under 100 nm models and 81 % under 70 nm models. We also propose a transistor and pin reordering technique that has minimal layout impact to further reduce the total leakage current up to 12% and Igate up to 27% without incurring any delay penalty.

Original languageEnglish (US)
Pages (from-to)1362-1375
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number12
StatePublished - Dec 2005

Bibliographical note

Funding Information:
Manuscript received November 5, 2004; revised March 22, 2005 and June 3, 2005. This work was supported in part by the Semiconductor Research Corporation under Contract 2003-TJ-1092 and by the National Science Foundation under Award CCR-0205227. A. K. Sultania is with Calypto Design Systems Inc., Santa Clara, CA 95054 USA (e-mail: D. Sylvester is with the Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109 USA. S. S. Sapatnekar is with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA. Digital Object Identifier 10.1109/TVLSI.2005.862723


  • Dual oxide thicknesses
  • Gate leakage
  • Leakage power
  • Pin reordering
  • Power delay tradeoffs
  • Subthreshold leakage
  • Technology scaling
  • Transistor reordering


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