Hardware efficient fast computation of the discrete fourier transform

Chao Cheng, Keshab K Parhi

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

In this paper a new systolic array for prime N-length DFT is first proposed and then combined with Winograd Fourier Transform algorithm (WFTA) to control the increase of the hardware cost when the transform length is large. The proposed new DFT design is both fast and hardware efficient. Compared with the recently reported DFT design with computational complexity of O(log N) the proposed design saves the average number of required multiplications by 30 to 60% and reduces the average computation time by more than 2 times when the transform length changes from 16 to 2048.

Original languageEnglish (US)
Pages (from-to)159-171
Number of pages13
JournalJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
Volume42
Issue number2
DOIs
StatePublished - Feb 2006

Keywords

  • Cyclic convolution
  • Discrete fourier transform
  • Systolic array
  • Winograd Fourier Transform algorithm

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