Hardware efficient mixed radix-25/16/9 FFT for LTE systems

Jienan Chen, Jianhao Hu, Shuyang Lee, Gerald E. Sobelman

Research output: Contribution to journalArticlepeer-review

42 Scopus citations

Abstract

In this paper, we propose a hardware-efficient mixed generalized high-radix (GHR) reconfigurable fast Fourier transform (FFT) processor for long-term evolution applications. The GHR processor based on radix-25/16/9 uses a 2-D factorization scheme as the high-radix unit and a 1-D factorization method as the system data routing technology. The 2-D factorization scheme is implemented by an enhanced delay element matrix structure, which supports 25-, 16-, 9-, 8-, 5-, 4-, 3-, and 2-point FFTs. Two different designs were implemented. One design (called discrete Fourier transform core) supports 34 different transform sizes from 12 to 1296 points, while the other design (called FFT core) supports five different power-of-two sizes from 128 to 2048 points. The 1-D factorization method is performed by a coprime accessing technology, which accesses the data in parallel without conflict using a RAM. The GHR combines 2-D and 1-D factorization techniques and improves the throughput by a factor of two to four with comparable hardware cost compared with the previous designs. The speed-area ratio of the proposed scheme is nearly two times better than that of previous FFT processors. Application-specified integrated circuit implementation results based on a 0.18-μ m technology are also provided.

Original languageEnglish (US)
Article number6755459
Pages (from-to)221-229
Number of pages9
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume23
Issue number2
DOIs
StatePublished - Feb 1 2015

Keywords

  • Fast Fourier transforms (FFTs)
  • Reconfigurable.
  • generalized high radix (GHR)
  • long-term evolution (LTE)

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