Hierarchical analysis of power distribution networks

Min Zhao, Rajendran V. Panda, Sachin S. Sapatnekar, David Blaauw

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165 Scopus citations


Careful design and verification of the power distribution network of a chip are of critical importance to ensure its reliable performance. With the increasing number of transistors on a chip, the size of the power network has grown so large as to make the verification task very challenging. The available computational power and memory resources impose limitations on the size of networks that can be analyzed using currently known techniques. Many of today's designs have power networks that are too large to be analyzed in the traditional way as flat networks. In this paper, we propose a hierarchical analysis technique to overcome the aforesaid capacity limitation. We present a new technique for analyzing a power grid using macromodels that are created for a set of partitions of the grid. Efficient numerical techniques for the computation and sparsification of the port admittance matrices of the macromodels are presented. A novel sparsification technique using a 0-1 integer linear programming formulation is proposed to achieve superior sparsification for a specified error. The run-time and memory efficiency of the proposed method are illustrated on industrial designs. It is shown that even for a 60 million-node power grid, our approach allows for an efficient analysis, whereas previous approaches have been unable to handle power grids of such size.

Original languageEnglish (US)
Pages (from-to)159-168
Number of pages10
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number2
StatePublished - Feb 2002

Bibliographical note

Funding Information:
Manuscript received May 30, 2001. This work was supported in part by the Semiconductor Research Corporation under contract number 99-TJ-714 and by the National Science Foundation under contract number CCR-9800992. This paper was recommended by Associate Editor E. Macii. M. Zhao and R. V. Panda are with Motorola SPS, Austin, TX 78729 USA (e-mail: zhao@adttx.sps.mot.com). S. S. Sapatnekar is with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA. D. Blaauw is with the Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109 USA. Publisher Item Identifier S 0278-0070(02)01055-2.


  • Circuit simulation
  • IR drop
  • Matrix sparsification
  • Partitioning
  • Power distribution networks
  • Power grid
  • Signal integrity


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