Hierarchical random-walk algorithms for power grid analysis

Haifeng Qian, Sachin S. Sapatnekar

Research output: Contribution to conferencePaperpeer-review

36 Scopus citations

Abstract

This paper presents a power grid analyzer that combines a divide-and-conquer strategy with a random-walk engine. A single-level hierarchical method is first described and then extended to multi-level and "virtual-layer" hierarchy. Experimental results show that these algorithms not only achieve speedups over the generic random-walk method, but also are more robust in solving various types of industrial circuits. For example, a 71K-node circuit is solved in 4.16 seconds, showing a more than 4 times speedup over the generic method; a 348K-node wire-bond power grid, for which the performance of the generic method degrades, is solved in 75.88 seconds.

Original languageEnglish (US)
Pages499-504
Number of pages6
DOIs
StatePublished - Jan 1 2004
EventProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama, Japan
Duration: Jan 27 2004Jan 30 2004

Other

OtherProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004
Country/TerritoryJapan
CityYokohama
Period1/27/041/30/04

Fingerprint

Dive into the research topics of 'Hierarchical random-walk algorithms for power grid analysis'. Together they form a unique fingerprint.

Cite this