High-efficiency, Ge-on-SOI lateral PIN photodiodes with 29 GHz bandwidth

S. J. Koester; J. D. Schaub; G. Dehlinger; J. O. Chu; Q. C. Ouyang; A. Grill

doi:10.1109/DRC.2004.1367846

High-efficiency, Ge-on-SOI lateral PIN photodiodes with 29 GHz bandwidth

S. J. Koester, J. D. Schaub, G. Dehlinger, J. O. Chu, Q. C. Ouyang, A. Grill

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

19 Scopus citations

Abstract

The lateral PIN photodetectors were fabricated using Ge films deposited on ultra-thin silicon-on-insulator (SOI) substrates. The starting material was produced by directly growing Ge on a thin SOI substrate with initial SOI thickness of 15 nm. Good agreement between theory and experiment was obtained, demonstrating the benefit of the SOI layer for limiting the Si and Ge interdiffusion during high-temperature thermal cyclic annealing (TCA) step. The bandwidth saturated at very low voltages, and even at zero bias, bandwidths as high as 20 GHz were achieved.

Original language	English (US)
Title of host publication	Device Research Conference - Conference Digest, 62nd DRC
Pages	175-176
Number of pages	2
DOIs	https://doi.org/10.1109/DRC.2004.1367846
State	Published - Dec 1 2004
Event	Device Research Conference - Conference Digest, 62nd DRC - Notre Dame, IN, United States Duration: Jun 21 2004 → Jun 23 2004

Other

Other	Device Research Conference - Conference Digest, 62nd DRC
Country/Territory	United States
City	Notre Dame, IN
Period	6/21/04 → 6/23/04

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Koester, SJ, Schaub, JD, Dehlinger, G, Chu, JO, Ouyang, QC & Grill, A 2004, High-efficiency, Ge-on-SOI lateral PIN photodiodes with 29 GHz bandwidth. in Device Research Conference - Conference Digest, 62nd DRC., V.A.-4, pp. 175-176, Device Research Conference - Conference Digest, 62nd DRC, Notre Dame, IN, United States, 6/21/04. https://doi.org/10.1109/DRC.2004.1367846

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abstract = "The lateral PIN photodetectors were fabricated using Ge films deposited on ultra-thin silicon-on-insulator (SOI) substrates. The starting material was produced by directly growing Ge on a thin SOI substrate with initial SOI thickness of 15 nm. Good agreement between theory and experiment was obtained, demonstrating the benefit of the SOI layer for limiting the Si and Ge interdiffusion during high-temperature thermal cyclic annealing (TCA) step. The bandwidth saturated at very low voltages, and even at zero bias, bandwidths as high as 20 GHz were achieved.",

author = "Koester, {S. J.} and Schaub, {J. D.} and G. Dehlinger and Chu, {J. O.} and Ouyang, {Q. C.} and A. Grill",

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AU - Koester, S. J.

AU - Schaub, J. D.

AU - Dehlinger, G.

AU - Chu, J. O.

AU - Ouyang, Q. C.

AU - Grill, A.

PY - 2004/12/1

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N2 - The lateral PIN photodetectors were fabricated using Ge films deposited on ultra-thin silicon-on-insulator (SOI) substrates. The starting material was produced by directly growing Ge on a thin SOI substrate with initial SOI thickness of 15 nm. Good agreement between theory and experiment was obtained, demonstrating the benefit of the SOI layer for limiting the Si and Ge interdiffusion during high-temperature thermal cyclic annealing (TCA) step. The bandwidth saturated at very low voltages, and even at zero bias, bandwidths as high as 20 GHz were achieved.

AB - The lateral PIN photodetectors were fabricated using Ge films deposited on ultra-thin silicon-on-insulator (SOI) substrates. The starting material was produced by directly growing Ge on a thin SOI substrate with initial SOI thickness of 15 nm. Good agreement between theory and experiment was obtained, demonstrating the benefit of the SOI layer for limiting the Si and Ge interdiffusion during high-temperature thermal cyclic annealing (TCA) step. The bandwidth saturated at very low voltages, and even at zero bias, bandwidths as high as 20 GHz were achieved.

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High-efficiency, Ge-on-SOI lateral PIN photodiodes with 29 GHz bandwidth

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