High level DSP synthesis using the MARS design system

In this paper we address methodologies for high-level synthesis of dedicated digital signal processing (DSP) architectures using the Minesota ARchitecture Synthesis (MARS) design system. We present new concurrent scheduling and resource allocation algorithms which exploit interiteration and intra-iteration precedence constraints. These novel algorithms produce solutions which are as good as or better than those previously published. Previous synthesis systems have focused on DSP algorithms which have single or lumped delays in the recursive loops. MARS is capable of generating valid architectures for algorithms which have distributed arc delays arid exploits these delays to produce more efficient architectures. This allows our system to be more general and provides for the synthesis of more complicated algorithms. Our system utilizes implicit retiming and pipelining of the data flow graph to improve the quality of the design. We are able to synthesize architectures which meet the iteration bound of any algorithm by unfolding the original data flow graph.