High linearity PVT tolerant 100MS/s rail-to-rail ADC driver with built-in sampler in 65nm CMOS

Rakesh Kumar Palani; Ramesh Harjani

doi:10.1109/CICC.2014.6946065

High linearity PVT tolerant 100MS/s rail-to-rail ADC driver with built-in sampler in 65nm CMOS

Rakesh Kumar Palani, Ramesh Harjani

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Scopus citations

Abstract

A novel completely inverter-based ADC driver is proposed that relaxes the gain and unity gain bandwidth requirements of the negative feedback loop by making it not see the closed loop gain. This ADC driver has a built-in first order anti alias filter and uses a passive amplifier to provide a rail-to-rail sampled output signal. This design exploits the linearity of current mirrors and achieves 65dB of linearity at the Nyquist rate for a rail-to-rail output. A semi-constant current biasing circuit for inverters has been proposed to minimizing PVT variations in lower technologies. As a proof of concept an ADC driver is designed and implemented in TSMC's 65nm GP CMOS technology. The measured design operates at 100MS/s and has an OIP₃ of 40dBm at the Nyquist rate, provides a gain of 8, and samples the signal onto a 1pF output capacitance while drawing 2mA from a 1V supply.

Original language	English (US)
Title of host publication	Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479932863
DOIs	https://doi.org/10.1109/CICC.2014.6946065
State	Published - Nov 4 2014
Event	36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014 - San Jose, United States Duration: Sep 15 2014 → Sep 17 2014

Publication series

Name	Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014

Other

Other	36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014
Country/Territory	United States
City	San Jose
Period	9/15/14 → 9/17/14

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

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10.1109/CICC.2014.6946065

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Palani, R. K., & Harjani, R. (2014). High linearity PVT tolerant 100MS/s rail-to-rail ADC driver with built-in sampler in 65nm CMOS. In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014 Article 6946065 (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2014.6946065

High linearity PVT tolerant 100MS/s rail-to-rail ADC driver with built-in sampler in 65nm CMOS. / Palani, Rakesh Kumar; Harjani, Ramesh.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014. Institute of Electrical and Electronics Engineers Inc., 2014. 6946065 (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Palani, RK & Harjani, R 2014, High linearity PVT tolerant 100MS/s rail-to-rail ADC driver with built-in sampler in 65nm CMOS. in Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014., 6946065, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014, Institute of Electrical and Electronics Engineers Inc., 36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014, San Jose, United States, 9/15/14. https://doi.org/10.1109/CICC.2014.6946065

Palani RK, Harjani R. High linearity PVT tolerant 100MS/s rail-to-rail ADC driver with built-in sampler in 65nm CMOS. In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014. Institute of Electrical and Electronics Engineers Inc. 2014. 6946065. (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014). doi: 10.1109/CICC.2014.6946065

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High linearity PVT tolerant 100MS/s rail-to-rail ADC driver with built-in sampler in 65nm CMOS

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