Concurrent fine-grain pipelined VLSI architectures for dynamic programming (DP) problems are presented. Look-ahead is used to obtain finer-grain pipelining, and a novel precomputation sequence is used to design DP computation architectures with square to linear add-compare-select (ACS) processor complexity (in number of states in the DP problem). Use of nonuniform pipelining and nonuniform implementation methodologies in dedicated DP architectures is introduced; this results in a saving of hardware modules with no loss in speed. A two's complement least-significant-bit-first bit-serial architecture is also presented for the compare-select operation.
|Original language||English (US)|
|Number of pages||4|
|Journal||ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings|
|State||Published - Dec 1 1990|
|Event||1990 International Conference on Acoustics, Speech, and Signal Processing: Speech Processing 2, VLSI, Audio and Electroacoustics Part 2 (of 5) - Albuquerque, New Mexico, USA|
Duration: Apr 3 1990 → Apr 6 1990