This brief presents a high-speed parallel cyclic redundancy check (CRC) implementation based on unfolding, pipelining, and retiming algorithms. CRC architectures are first pipelined to reduce the iteration bound by using novel look-ahead pipelining methods and then unfolded and retimed to design high-speed parallel circuits. A comparison on commonly used generator polynomials between the proposed design and previously proposed parallel CRC algorithms shows that the proposed design can increase the speed by up to 25% and control or even reduce hardware cost.
|Original language||English (US)|
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|State||Published - Oct 2006|
- Cyclic redundancy check (CRC)
- linear feedback shift register (LFSR)
- retiming unfolding