High speed VLSI architecture for general linear feedback shift register (LFSR) structures

Chao Cheng; Keshab K Parhi

doi:10.1109/ACSSC.2009.5469943

High speed VLSI architecture for general linear feedback shift register (LFSR) structures

Chao Cheng, Keshab K Parhi

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

15 Scopus citations

Abstract

Based on previous three-step high-speed VLSI architecture for LFSR structures, this paper proposes an improved three-step LFSR architecture with both higher hardware efficiency and speed. Generator polynomials for the first and third steps are constructed with iterative small length polynomials, which can in turn be easily handled by proposed look-ahead pipelining algorithm. A new scheme is also proposed for cutting down the iteration bound of the LFSR structure in the second step. This architecture can be applied to any LFSR structure for high-speed parallel implementation. For example, for the parallel BCH (8191, 7684) encoder with different unfolding factors J from 8 to 32, the proposed design can achieve speedup of 2.83% to 15.78% and XOR gates savings of 9.67% to 26.28%.

Original language	English (US)
Title of host publication	Conference Record - 43rd Asilomar Conference on Signals, Systems and Computers
Pages	713-717
Number of pages	5
DOIs	https://doi.org/10.1109/ACSSC.2009.5469943
State	Published - Dec 1 2009
Event	43rd Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, United States Duration: Nov 1 2009 → Nov 4 2009

Other

Other	43rd Asilomar Conference on Signals, Systems and Computers
Country/Territory	United States
City	Pacific Grove, CA
Period	11/1/09 → 11/4/09

Keywords

BCH
CRC
Linear feedback shift register (lfsr)
VLSI

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10.1109/ACSSC.2009.5469943

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title = "High speed VLSI architecture for general linear feedback shift register (LFSR) structures",

abstract = "Based on previous three-step high-speed VLSI architecture for LFSR structures, this paper proposes an improved three-step LFSR architecture with both higher hardware efficiency and speed. Generator polynomials for the first and third steps are constructed with iterative small length polynomials, which can in turn be easily handled by proposed look-ahead pipelining algorithm. A new scheme is also proposed for cutting down the iteration bound of the LFSR structure in the second step. This architecture can be applied to any LFSR structure for high-speed parallel implementation. For example, for the parallel BCH (8191, 7684) encoder with different unfolding factors J from 8 to 32, the proposed design can achieve speedup of 2.83% to 15.78% and XOR gates savings of 9.67% to 26.28%.",

keywords = "BCH, CRC, Linear feedback shift register (lfsr), VLSI",

author = "Chao Cheng and Parhi, {Keshab K}",

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AB - Based on previous three-step high-speed VLSI architecture for LFSR structures, this paper proposes an improved three-step LFSR architecture with both higher hardware efficiency and speed. Generator polynomials for the first and third steps are constructed with iterative small length polynomials, which can in turn be easily handled by proposed look-ahead pipelining algorithm. A new scheme is also proposed for cutting down the iteration bound of the LFSR structure in the second step. This architecture can be applied to any LFSR structure for high-speed parallel implementation. For example, for the parallel BCH (8191, 7684) encoder with different unfolding factors J from 8 to 32, the proposed design can achieve speedup of 2.83% to 15.78% and XOR gates savings of 9.67% to 26.28%.

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KW - CRC

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High speed VLSI architecture for general linear feedback shift register (LFSR) structures

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