TY - GEN

T1 - High-speed VLSI arithmetic processor architectures using hybrid number representation

AU - Srinivas, H. R.

AU - Parhi, Keshab K.

PY - 1991/12/1

Y1 - 1991/12/1

N2 - This paper addresses the design of high-speed architectures for fixed-point, two's-complement, bit-parallel, pipelined, multiplication, division and square-root operations. Architectures presented here make use of hybrid number representations (i.e. the input and output numbers are represented using two's complement representation, and the internal numbers are represented using radix-2 redundant representation). We present a fast, new conversion scheme for converting radix-2 redundant numbers to two's-complement binary numbers, and use this to design a reduced latency bit-parallel multiplier. Our novel sign-multiplexing scheme helps detect the sign of a redundant number very quickly and is used in combination with the remainder conditioning scheme to achieve very high speed in fixed- point division and square-root operators. These architectures require fewer pipelining latches than their conventional two's-complement counterparts. Reduction in latency without sacrificing clock speed has resulted in reduced computation time for these operations.

AB - This paper addresses the design of high-speed architectures for fixed-point, two's-complement, bit-parallel, pipelined, multiplication, division and square-root operations. Architectures presented here make use of hybrid number representations (i.e. the input and output numbers are represented using two's complement representation, and the internal numbers are represented using radix-2 redundant representation). We present a fast, new conversion scheme for converting radix-2 redundant numbers to two's-complement binary numbers, and use this to design a reduced latency bit-parallel multiplier. Our novel sign-multiplexing scheme helps detect the sign of a redundant number very quickly and is used in combination with the remainder conditioning scheme to achieve very high speed in fixed- point division and square-root operators. These architectures require fewer pipelining latches than their conventional two's-complement counterparts. Reduction in latency without sacrificing clock speed has resulted in reduced computation time for these operations.

UR - http://www.scopus.com/inward/record.url?scp=0026297379&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026297379&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0026297379

SN - 0818622709

T3 - IEEE International Conference on Computer Design - VLSI in Computers and Processors

SP - 564

EP - 571

BT - IEEE International Conference on Computer Design - VLSI in Computers and Processors

PB - Publ by IEEE

T2 - Proceedings of the 1991 IEEE International Conference on Computer Design - VLSI in Computers and Processors - ICCD '91

Y2 - 14 October 1991 through 16 October 1991

ER -