In high-level synthesis, a data flow graph (DFG) description of an algorithm is mapped onto a register transfer level description of an architecture. Each node of the DFG is scheduled to a specific time and allocated to a processor. In this paper, we present new integer linear programming (ILP) models which generate a blocked schedule for a DFG with automatic retiming, pipelining, and unfolding while performing module selection and data format conversion. A blocked schedule is a schedule which overlaps multiple iterations of the DFG to guarantee a processor optimal schedule. During module selection an appropriate processor is chosen from a library of processors to construct a cost optimal architecture. Furthermore, we also include the cost and latency of data format conversions between processors of different implementation styles. We also present a new formulation for minimizing the unfolding factor of the blocked schedule. The approach presented in this paper is the only systematic approach proposed so far to include implicit unfolding and to perform synthesis using nonuniform processor styles and data format converters.
|Original language||English (US)|
|Number of pages||13|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Published - 1998|
Bibliographical noteFunding Information:
Manuscript received March 10, 1996; revised June 30, 1998. This work was supported by the Advanced Research Projects Agency under Contract F33615-93-C-1309. K. Ito is with the Department of Electrical and Electronic Systems, Saitama University, Urawa 338-8570 Japan. L. E. Lucke and K. K. Parhi are with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA. Publisher Item Identifier S 1063-8210(98)07213-8.
- Data format conversion
- High-level synthesis
- Integer linear programming
- Module selection
- Time-constrained scheduling