Implementation approaches for the advanced encryption standard algorithm

Zhang Xinmiao, Keshab K Parhi

Research output: Contribution to journalArticlepeer-review

88 Scopus citations

Abstract

This paper addresses various approaches for efficient hardware implementation of the Advanced Encryption Standard algorithm. The optimization methods can be divided into two classes: architectural optimization and algorithmic optimization. Architectural optimization exploits the strength of pipelining, loop unrolling and sub-pipelining. Speed is increased by processing multiple rounds simultaneously at the cost of increased area. Architectural optimization is not an effective solution in feedback mode. Loop unrolling is the only architecture that can achieve a slight speedup with significantly increased area. In non-feedback mode, sub-pipelining can achieve maximum speedup and the best speed/area ratio. Algorithmic optimization exploits algorithmic strength inside each round unit. Various methods to reduce the critical path and area of each round unit are presented. Resource sharing issues between encryptor and decryptor are also discussed. They become important issues when both encryptor and decryptor need to be implemented in a small area.

Original languageEnglish (US)
Pages (from-to)24-46
Number of pages23
JournalIEEE Circuits and Systems Magazine
Volume2
Issue number4
DOIs
StatePublished - 2002

Bibliographical note

Funding Information:
Xinmiao Zhang and Keshab K. Parhi are with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, Minnesota, 55455. E-mails: {jennizh, parhi}@ ece.umn.edu This work has been supported by the Army Research Office under grant number DA/DAAD 19-01-1-0705.

Keywords

  • Advanced encryption standard
  • Key expansion
  • Loop unrolling
  • Pipelining
  • Rijndael
  • S-box
  • Substructure sharing

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