This paper focuses on designing elliptic curve crypto-accelerators in GF (2 m) that are cryptographically scalable and hold some degree of reconfigurability. Previous work in elliptic curve crypto-accelerators focused on implementations using projective coordinate systems for specific field sizes. Their performance, scalar point multiplication per second (kP/s), was determined primarily by the underlying multiplier implementation. In addition, a multiplier only implementation and a multiplier plus divider implementation are compared in terms of critical path, area, and area time (AT) product Our multiplier only design, designed for high performance, can achieve 6314 kP/s for GF(2 571) and requires 47876 LUTs. Meanwhile our multiplier and divider design, with a greater degree of reconflgurability, can achieve 44 kP/s for GF(2 571). However, this design requires 27355 LUTs, and has a significantly higher AT product. It is shown that reconfigurability with the reduction polynomial significantly benefits from the addition of a low latency divider unit and scalar point multiplication in affine coordinates. In both cases the performance is limited by a critical path in the control logic.
|Original language||English (US)|
|Number of pages||7|
|Journal||Conference Record - Asilomar Conference on Signals, Systems and Computers|
|State||Published - Dec 1 2004|
|Event||Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, United States|
Duration: Nov 7 2004 → Nov 10 2004