Abstract
The effects of gate structure design on RF performance of strained-Si/SiGe nMODFETs are studied using device simulation and experiments. It is found that while gate resistance only affects fmax, fringing gate capacitance can have a significant impact on both fT and fmax, indicating that the physical gate structure has to be optimized for any specific application. The experiments suggest that low-ic material is needed as sidewall spacer (if any) and passivation for reducing fringing gate capacitance. Furthermore, the simulations show that if low gate resistance can be achieved by using a multi-finger geometry, a rectangular-shaped gate should be used in order to reduce fringing gate capacitance. If not, a T-gate should be used to reduce gate resistance for high fmax.
Original language | English (US) |
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Title of host publication | SISPAD 2003 - 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 203-206 |
Number of pages | 4 |
ISBN (Electronic) | 0780378261 |
DOIs | |
State | Published - 2003 |
Event | 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2003 - Boston, United States Duration: Sep 3 2003 → Sep 5 2003 |
Publication series
Name | International Conference on Simulation of Semiconductor Processes and Devices, SISPAD |
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Volume | 2003-January |
Other
Other | 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2003 |
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Country/Territory | United States |
City | Boston |
Period | 9/3/03 → 9/5/03 |
Bibliographical note
Publisher Copyright:© 2003 IEEE.
Keywords
- CMOS technology
- Capacitance
- Etching
- Germanium silicon alloys
- HEMTs
- Immune system
- MODFETs
- Passivation
- Radio frequency
- Silicon germanium