@inproceedings{7ada503eea2545bf8bb1e3ebb396d238,
title = "Implications of gate design on RF performance of sub-100 nm strained-Si/SiGe nMODFETs",
abstract = "The effects of gate structure design on RF performance of strained-Si/SiGe nMODFETs are studied using device simulation and experiments. It is found that while gate resistance only affects fmax, fringing gate capacitance can have a significant impact on both fT and fmax, indicating that the physical gate structure has to be optimized for any specific application. The experiments suggest that low-ic material is needed as sidewall spacer (if any) and passivation for reducing fringing gate capacitance. Furthermore, the simulations show that if low gate resistance can be achieved by using a multi-finger geometry, a rectangular-shaped gate should be used in order to reduce fringing gate capacitance. If not, a T-gate should be used to reduce gate resistance for high fmax.",
keywords = "CMOS technology, Capacitance, Etching, Germanium silicon alloys, HEMTs, Immune system, MODFETs, Passivation, Radio frequency, Silicon germanium",
author = "Q. Ouyang and Koester, {S. J.} and Chu, {J. O.} and Saenger, {K. L.} and Ott, {J. A.} and Jenkins, {K. A.}",
year = "2003",
month = jan,
day = "1",
doi = "10.1109/SISPAD.2003.1233672",
language = "English (US)",
series = "International Conference on Simulation of Semiconductor Processes and Devices, SISPAD",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "203--206",
booktitle = "SISPAD 2003 - 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices",
note = "2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2003 ; Conference date: 03-09-2003 Through 05-09-2003",
}