Improving energy and performance with spintronics caches in multicore systems

William Tuohy, Cong Ma, Pushkar Nandkar, Nishant Borse, David J. Lilja

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Spintronic memory (STT-MRAM) is an attractive alternative technology to CMOS since it offers higher density and virtually no leakage current. Spintronic memory continues to require higher write energy, however, presenting a challenge to memory hierarchy design when energy consumption is a concern. Various techniques for reducing write energy have been studied in the past for a single processor, typically focusing on the last-level caches while keeping the first level caches in CMOS to avoid the write latency. In this work, use of STT-MRAM for the first level caches of a multicore processor is motivated by showing that the impact on throughput due to increased write latency is offset in many cases by increased cache size due to higher density. The Parsec benchmark suite is run on a modern multicore platform simulator, comparing performance and energy consumption of the spintronic cache system to a CMOS design. A small, fully-associative level-0 cache is then introduced (on the order of 8-64 cache lines), and shown to effectively hide the STT-MRAM write latency. Performance degradation due to write latency is restored or slightly improved, while cache energy consumption is reduced by 30-50% for 12 of the 13 benchmarks.

Original languageEnglish (US)
Title of host publicationEuro-Par 2014
Subtitle of host publicationParallel Processing Workshops - Euro-Par 2014 InternationalWorkshops, Revised Selected Papers
EditorsLuís Lopes
PublisherSpringer- Verlag
Number of pages12
ISBN (Electronic)9783319143125
StatePublished - Jan 1 2014
EventInternational Workshop on Parallel Processing, Euro-Par 2014 - Porto, Portugal
Duration: Aug 25 2014Aug 26 2014

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


OtherInternational Workshop on Parallel Processing, Euro-Par 2014


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