InAs/SiGe on Si nanowire tunneling field effect transistors

Tunneling field-effect transistors (TFETs) are of tremendous interest for advanced logic applications due to their potential for sub-60-mV/dec subthreshold slope which could enable supply voltage scaling beyond what is practical for conventional MOSFETs. However, TFETs based upon tunneling in Si suffer from low on current, I_ON, and fail to provide steep slope at high current levels. III-V TFETs are more promising due to their potential for high drive current, but the poor gate oxide quality remains a significant challenge. Recently, a hybrid III-V-on-Si approach [1] has been proposed as a potential solution to this problem, whereby the small effective band gap, E _geff, of the InAs/Si heterojunction could increase I_ON, while preserving the high-quality Si/dielectric interface in the channel. Experimental demonstrations of nanostructured InAs-on-Si Esaki diodes and TFETs suggest this approach is feasible [1],[2]. However, InAs-on-Si heterostructures still exhibit relatively large E_geff (∼ 0.4 eV in unconfined geometries) and quantum effects increase E_geff substantially in confined geometries. In this paper, we provide a simulation analysis of a new device structure, the InAs/SiGe/Si TFET that could overcome this problem by utilizing a compressivelystrained SiGe layer to further decrease E _geff. We show that I_ON in these devices increases by 5× (at constant I_off) and further explore the various trade-offs and performance-limiting factors in these devices.