Integrated amplifier architectures for efficient coupling to the nervous system

Timothy Denison, Gregory Molnar, Reid R. Harrison

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Monitoring the electrical activity of multiple neurons in the brain could enable a wide range of scientific and clinical endeavors. An enabling technology for neural monitoring is the interface amplifier. Current amplifier research is focused on two paradigms of chronically sensing neural activity: one is the measurement of 'spike' signals from individual neurons to provide high-fidelity control signals for neuroprosthesis, while the other is the measurement of bandpower fluctuations from cell ensembles that convey general information like the intention to move. In both measurement techniques, efforts to merge neural recording arrays with integrated electronics have revealed significant circuit design challenges. For example, weak neural signals, on the order of tens of microvolts rms, must be amplified prior to analysis and are often co-located with frequencies dominated by 1/f and popcorn noise in CMOS technologies. To insure the highest fidelity measurement, micropower chopper stabilization is often required to provide immunity from this excess noise. Another difficulty is that strict power constraints place severe limitations on the signal processing, algorithms and telemetry capabilities available in a practical system. These constraints motivate the design of the interface amplifier as part of a total system-level solution. In particular, the system solutions we pursued are driven by the key neural signal of interest, and we use the characteristics of the neural code guide the partitioning of the signal chain. To illustrate the generality of this design philosophy, we discuss state-of-the-art design examples from a spike-based, single-cell system, and a field potential, ensemble neuronal measurement system, both intended for practical and robust neuroprosthesis applications.

Original languageEnglish (US)
Title of host publicationAnalog Circuit Design - High-Speed Clock and Data Recovery, High-Performance Amplifiers, Power Management
PublisherSpringer London
Pages167-191
Number of pages25
ISBN (Print)9781402089435
DOIs
StatePublished - 2009
Event17th Workshop on Advances in Analog Circuit Design, AACD 2008 - Pavia, Italy
Duration: Apr 8 2008Apr 10 2008

Publication series

NameAnalog Circuit Design - High-Speed Clock and Data Recovery, High-Performance Amplifiers, Power Management

Other

Other17th Workshop on Advances in Analog Circuit Design, AACD 2008
Country/TerritoryItaly
CityPavia
Period4/8/084/10/08

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