TY - GEN
T1 - Interconnect design using convex optimization
AU - Sancheti, Piyush K.
AU - Sapatnekar, Sachin S.
PY - 1994/1/1
Y1 - 1994/1/1
N2 - Two wire sizing formulations for optimizing interconnect are presented. The first minimizes the delay under wire width constraints, while the second minimizes the wiring area under delay and width constraints. A convex programming formulation is proposed, and an efficient algorithm is used to perform the optimization. Experimental results show that the first formulation, which has been the prevalent one in the literature, provides bad engineering solutions, and that the second formulation leads to significantly better results.
AB - Two wire sizing formulations for optimizing interconnect are presented. The first minimizes the delay under wire width constraints, while the second minimizes the wiring area under delay and width constraints. A convex programming formulation is proposed, and an efficient algorithm is used to perform the optimization. Experimental results show that the first formulation, which has been the prevalent one in the literature, provides bad engineering solutions, and that the second formulation leads to significantly better results.
UR - http://www.scopus.com/inward/record.url?scp=0027940784&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0027940784&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0027940784
SN - 0780318870
T3 - Proceedings of the Custom Integrated Circuits Conference
SP - 549
EP - 552
BT - Proceedings of the Custom Integrated Circuits Conference
A2 - Anon, null
PB - Publ by IEEE
T2 - Proceedings of the IEEE 1994 Custom Integrated Circuits Conference
Y2 - 1 May 1994 through 4 May 1994
ER -