TY - GEN
T1 - Interleaving of gate sizing and constructive placement for predictable performance
AU - Kim, Sungjae
AU - Shragowitz, Eugene
AU - Karypis, George
AU - Lin, Rung Bin
PY - 2007/9/28
Y1 - 2007/9/28
N2 - This paper presents a fast fixed-die standard cell placement algorithm. Placement is achieved by a combination of top-down partitioning with the incremental row-by-row construction. This paper concentrates on the construction part of this process. Gate sizing is interleaved with the placement construction process. Before placement, every gate is given its minimal size. During the placement, gates are resized to satisfy the timing constraints. Behavior of the placement is adapted based on dynamically recomputed net delay bounds. Experimental results show significant improvement in timing, predictability of results, and run time with respect to a commercial placement tool.
AB - This paper presents a fast fixed-die standard cell placement algorithm. Placement is achieved by a combination of top-down partitioning with the incremental row-by-row construction. This paper concentrates on the construction part of this process. Gate sizing is interleaved with the placement construction process. Before placement, every gate is given its minimal size. During the placement, gates are resized to satisfy the timing constraints. Behavior of the placement is adapted based on dynamically recomputed net delay bounds. Experimental results show significant improvement in timing, predictability of results, and run time with respect to a commercial placement tool.
UR - http://www.scopus.com/inward/record.url?scp=34648824880&partnerID=8YFLogxK
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U2 - 10.1109/VDAT.2007.373225
DO - 10.1109/VDAT.2007.373225
M3 - Conference contribution
AN - SCOPUS:34648824880
SN - 1424405831
SN - 9781424405831
T3 - 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
BT - 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
T2 - 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007
Y2 - 25 April 2007 through 27 April 2007
ER -