Introduction

Taehyoun Oh, Ramesh Harjani

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

Rapid advances in CMOS technology continue to increase the on-chip clock speeds exponentially, while high-speed I/Os that are used to connect between chips continue to be a performance bottleneck for the system. Finite channel bandwidths generate ISI and reduce the amplitude of the received signal and thus degrade SNR.

Original languageEnglish (US)
Title of host publicationAnalog Circuits and Signal Processing
PublisherSpringer
Pages1-9
Number of pages9
DOIs
StatePublished - 2014

Publication series

NameAnalog Circuits and Signal Processing
ISSN (Print)1872-082X
ISSN (Electronic)2197-1854

Bibliographical note

Publisher Copyright:
© 2014, Springer Science+Business Media New York.

Keywords

  • Adjacent Channel
  • Crosstalk Signal
  • Differential Pair
  • Power Supply Rejection Ratio
  • Pulse Response

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