Introduction

Taehyoun Oh; Ramesh Harjani

doi:10.1007/978-1-4614-4963-8_1

Introduction

Taehyoun Oh, Ramesh Harjani

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

Rapid advances in CMOS technology continue to increase the on-chip clock speeds exponentially, while high-speed I/Os that are used to connect between chips continue to be a performance bottleneck for the system. Finite channel bandwidths generate ISI and reduce the amplitude of the received signal and thus degrade SNR.

Original language	English (US)
Title of host publication	Analog Circuits and Signal Processing
Publisher	Springer
Pages	1-9
Number of pages	9
DOIs	https://doi.org/10.1007/978-1-4614-4963-8_1
State	Published - 2014

Publication series

Name	Analog Circuits and Signal Processing
ISSN (Print)	1872-082X
ISSN (Electronic)	2197-1854

Bibliographical note

Publisher Copyright:
© 2014, Springer Science+Business Media New York.

Keywords

Adjacent Channel
Crosstalk Signal
Differential Pair
Power Supply Rejection Ratio
Pulse Response

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KW - Differential Pair

KW - Power Supply Rejection Ratio

KW - Pulse Response

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Introduction

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