Jitter Suppression Techniques for High-Speed Sample-and-Hold Circuits

In this paper, we discuss the limitations of the existing clock jitter reduction techniques, and introduce ΔΣ sampling, which can reduce the jitter-induced sampling error significantly. We investigate various feedback configurations, and show that NRZ and RZ feedback techniques both improve the jitter shaping properties of the ΔΣ sampler. However, in order to benefit from the superior jitter shaping, a constant feedback pulsewidth is required. We propose a new clocking scheme, called correlated clocking to address the feedback pulsewidth variations. This technique utilizes the correlation between the rising and falling edges of the on-chip clocks to eliminate the feedback pulsewidth jitter. We show that a 1^st -order ΔΣ sampler with correlated RZ feedback can achieve the same SJNR as a ΔΣ sampler with switched-capacitor feedback. We then expand our analysis to 2^nd - and higher-order modulators, and show that contrary to common belief, even with constant-pulsewidth feedback, higher-order modulators are limited by the feedback pulse jitter. We conclude that the maximum benefit of a ΔΣ sampler with a conventional single-loop architecture is independent of the loop order, feedback mechanism, and the oversampling ratio, and it reaches 4.77 dB for OSR≥5.