Joint (3, k)-Regular LDPC Code and Decoder/Encoder Design

Tong Zhang, Keshab K. Parhi

Research output: Contribution to journalArticlepeer-review

59 Scopus citations


Recently, low-density parity-check (LDPC) codes have attracted a lot of attention in the coding theory community. However, their real-world applications are still problematic mainly due to the lack of effective decoder/encoder hardware design approaches. In this paper, we present a joint (3, k)-regular LDPC code and decoder/encoder design technique to construct a class of (3, k)-regular LDPC codes that not only have very good error-correcting capability but also exactly fit to high-speed partly parallel decoder and low-complexity encoder implementations. We also develop two techniques to further modify this joint design scheme to achieve more flexible tradeoffs between decoder hardware complexity and decoding speed.

Original languageEnglish (US)
Pages (from-to)1065-1079
Number of pages15
JournalIEEE Transactions on Signal Processing
Issue number4
StatePublished - Apr 2004


  • Architecture
  • Decoding
  • Encoding
  • Low-density parity check

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