Abstract
Recently, a low-latency decoding scheme called the simplified successive cancellation (SSC) algorithm has been proposed for polar codes. In this brief, we present the first systematic approach to formally derive the SSC decoding latency for any given polar code. The method to derive the SSC polar decoder architecture for any specific code is also presented. Moreover, the architecture of the precomputation SSC polar decoder is also proposed, which can further reduce the decoding latency. Compared with their SC decoder counterparts, the proposed SSC and precomputation SSC polar decoders can save up to 39.6% decoding latency with the same hardware cost.
Original language | English (US) |
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Article number | 6680761 |
Pages (from-to) | 115-119 |
Number of pages | 5 |
Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
Volume | 61 |
Issue number | 2 |
DOIs | |
State | Published - Feb 2014 |
Keywords
- Binary tree
- Data-flow graph (DFG)
- Polar codes
- Precomputation
- Simplified successive cancellation (SSC)