Layout-aware analog system synthesis based on symbolic layout description and combined block parameter exploration, placement and global routing

Hua Tang, Hui Zhang, Alex Doboli

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

This paper presents a new methodology for layout-aware synthesis of analog systems. The methodology combines block parameter exploration, block placement and global interconnect routing while maintaining an accurate perspective on the layout parasitics. An original system representation (called Layout Constraint Graphs - LCG) was developed for synthesis. The paper discusses how block parameter exploration, placement and global routing are expressed in terms of the LCG graph. AC and transient performances of each explored solution are obtained using SPICE simulations. Experiments show the generality of the synthesis methodology by providing results for several applications including filters and converters.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publicationNew Trends and Technologies for VLSI Systems Design, ISVLSI 2003
EditorsNagarajan Ranganathan, Asim Smailagic
PublisherIEEE Computer Society
Pages266-271
Number of pages6
ISBN (Electronic)0769519040
DOIs
StatePublished - Jan 1 2003
EventIEEE Computer Society Annual Symposium on VLSI, ISVLSI 2003 - Tampa, United States
Duration: Feb 20 2003Feb 21 2003

Publication series

NameProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume2003-January
ISSN (Print)2159-3469
ISSN (Electronic)2159-3477

Conference

ConferenceIEEE Computer Society Annual Symposium on VLSI, ISVLSI 2003
CountryUnited States
CityTampa
Period2/20/032/21/03

Keywords

  • Circuit simulation
  • Circuit synthesis
  • Design automation
  • Design optimization
  • Integrated circuit interconnections
  • Laboratories
  • Routing
  • SPICE
  • Signal synthesis
  • Wire

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