@inproceedings{ecc9827c86dd48c0bda24441d7420934,
title = "Layout-aware analog system synthesis based on symbolic layout description and combined block parameter exploration, placement and global routing",
abstract = "This paper presents a new methodology for layout-aware synthesis of analog systems. The methodology combines block parameter exploration, block placement and global interconnect routing while maintaining an accurate perspective on the layout parasitics. An original system representation (called Layout Constraint Graphs - LCG) was developed for synthesis. The paper discusses how block parameter exploration, placement and global routing are expressed in terms of the LCG graph. AC and transient performances of each explored solution are obtained using SPICE simulations. Experiments show the generality of the synthesis methodology by providing results for several applications including filters and converters.",
keywords = "Circuit simulation, Circuit synthesis, Design automation, Design optimization, Integrated circuit interconnections, Laboratories, Routing, SPICE, Signal synthesis, Wire",
author = "Hua Tang and Hui Zhang and Alex Doboli",
year = "2003",
month = jan,
day = "1",
doi = "10.1109/ISVLSI.2003.1183495",
language = "English (US)",
series = "Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI",
publisher = "IEEE Computer Society",
pages = "266--271",
editor = "Nagarajan Ranganathan and Asim Smailagic",
booktitle = "Proceedings - IEEE Computer Society Annual Symposium on VLSI",
note = "IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2003 ; Conference date: 20-02-2003 Through 21-02-2003",
}