Leakage in nano-scale technologies: Mechanisms, impact and design considerations

Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

49 Scopus citations

Abstract

The high leakage current in nano-meter regimes is becoming a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness are scaled. Consequently, the identification of different leakage components is very important for estimation and reduction of leakage. Moreover, the increasing statistical variation in the process parameters has led to significant variation in the transistor leakage current across and within different dies. Designing with the worst case leakage may cause excessive guard-banding, resulting in a lower performance. This paper explores various intrinsic leakage mechanisms including weak inversion, gate-oxide tunneling and junction leakage etc. Various circuit level techniques to reduce leakage energy and their design trade-off are discussed. We also explore process variation compensating techniques to reduce delay and leakage spread, while meeting power constraint and yield.

Original languageEnglish (US)
Title of host publicationProceedings of the 41st Design Automation Conference
Pages6-11
Number of pages6
DOIs
StatePublished - Sep 20 2004
EventProceedings of the 41st Design Automation Conference - San Diego, CA, United States
Duration: Jun 7 2004Jun 11 2004

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Other

OtherProceedings of the 41st Design Automation Conference
Country/TerritoryUnited States
CitySan Diego, CA
Period6/7/046/11/04

Keywords

  • Circuit design
  • Leakage current
  • Process variation

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