Logic-compatible embedded DRAM design for memory intensive low power systems

Ki Chul Chun; Pulkit Jain; Chris H. Kim

doi:10.1109/ISCAS.2010.5537877

Logic-compatible embedded DRAM design for memory intensive low power systems

Ki Chul Chun, Pulkit Jain, Chris H. Kim

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Scopus citations

Abstract

Circuit techniques for enabling a low power logic-compatible embedded DRAM (eDRAM) are presented. A boosted 3T gain cell utilizes preferential storage node boosting to improve data retention time and increase read margin. A regulated bit-line write scheme is equipped with a steady-state storage node voltage monitor to overcome the data '1' write disturbance problem. An adaptive and die-to-die adjustable read reference bias generator is proposed to cope with PVT variations. Measurement data from 65nm test chips demonstrate a >1.0msec retention time at 0.9V, 85°C and a <100μW per Mb refresh power at 1.0V, 85°C which translates into a 50% reduction in static power compared to a power gated SRAM.

Original language	English (US)
Title of host publication	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publication	Nano-Bio Circuit Fabrics and Systems
Pages	277-280
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2010.5537877
State	Published - Aug 31 2010
Event	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France Duration: May 30 2010 → Jun 2 2010

Publication series

Name	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Other

Other	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
Country/Territory	France
City	Paris
Period	5/30/10 → 6/2/10

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10.1109/ISCAS.2010.5537877

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Chun, K. C., Jain, P., & Kim, C. H. (2010). Logic-compatible embedded DRAM design for memory intensive low power systems. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 277-280). Article 5537877 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5537877

Logic-compatible embedded DRAM design for memory intensive low power systems. / Chun, Ki Chul; Jain, Pulkit; Kim, Chris H.
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 277-280 5537877 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chun, KC, Jain, P & Kim, CH 2010, Logic-compatible embedded DRAM design for memory intensive low power systems. in ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537877, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, pp. 277-280, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, France, 5/30/10. https://doi.org/10.1109/ISCAS.2010.5537877

Chun KC, Jain P, Kim CH. Logic-compatible embedded DRAM design for memory intensive low power systems. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 277-280. 5537877. (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). doi: 10.1109/ISCAS.2010.5537877

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Logic-compatible embedded DRAM design for memory intensive low power systems

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