TY - GEN
T1 - Logical effort based technology mapping
AU - Karandikar, Shrirang K.
AU - Sapatnekar, Sachin S
N1 - Copyright:
Copyright 2012 Elsevier B.V., All rights reserved.
PY - 2004
Y1 - 2004
N2 - We propose a new approach to library-based technology mapping, based on the method of logical effort. Our algorithm is close to optimal for fanout-free circuits, and is extended to solve the load-distribution problem for circuits with fanout. On average, benchmark circuits mapped using our approach are 25.39% faster than the solutions obtained from SIS.
AB - We propose a new approach to library-based technology mapping, based on the method of logical effort. Our algorithm is close to optimal for fanout-free circuits, and is extended to solve the load-distribution problem for circuits with fanout. On average, benchmark circuits mapped using our approach are 25.39% faster than the solutions obtained from SIS.
UR - http://www.scopus.com/inward/record.url?scp=16244404924&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=16244404924&partnerID=8YFLogxK
U2 - 10.1109/ICCAD.2004.1382611
DO - 10.1109/ICCAD.2004.1382611
M3 - Conference contribution
AN - SCOPUS:16244404924
SN - 0780387023
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
SP - 419
EP - 422
BT - ICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
T2 - ICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Y2 - 7 November 2004 through 11 November 2004
ER -