Low complexity implementations of sum-product algorithm for decoding low-density parity-check codes

Dacsun Oh, Keshab K Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Scopus citations

Abstract

In this paper, we propose low complexity implementations of sum-product algorithm (SPA) for decoding low-density parity-check (LDPC) codes. The finite precision implementations for SPA have an important tradeoff between the decoding performance and hardware complexity caused by two dominant area consuming factors. One is the memory for updated messages storage and the other is the look-up table (LUT) for implementation of nonlinear function ψ(x). The proposed two types of variable quantization schemes result in significant reductions of LUT sizes. Computer simulation results indicate that the performance losses of SPA with reduced LUT by proposed schemes are less than 0.05 dB compared to that of SPA with original LUT Moreover, the proposed implementation offers a large reduction in the finite wordlength for storage of updated messages using a kind of compression technique without performance losses. As a result, using the proposed implementation based on variable quantization scheme and data compression technique, the novel proposed implementation for SPA decoder architecture offers significant reductions of 75% and 33% in hardware complexities of LUT and memories, respectively, without significant performance degradations over conventional uniform quantization scheme. Furthermore, since each LUT with variable (6:3) quantization scheme II has only 8 entries, its hardware implementation can be replaced with a small combination circuit instead of read-only-memory (ROM) for LUT.

Original languageEnglish (US)
Title of host publication2006 IEEE Workshop on Signal Processing Systems Design and Implementation, SIPS
Pages262-267
Number of pages6
DOIs
StatePublished - Dec 1 2006
EventIEEE Workshop on Signal Processing Systems, SIPS 2006 - Banff, AB, Canada
Duration: Oct 2 2006Oct 4 2006

Other

OtherIEEE Workshop on Signal Processing Systems, SIPS 2006
Country/TerritoryCanada
CityBanff, AB
Period10/2/0610/4/06

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