Low-Energy deep belief networks using intrinsic sigmoidal spintronic-based probabilistic neurons

Ramtin Zand, Kerem Yunus Camsari, Steven D. Pyle, Ibrahim Ahmed, Chris H. Kim, Ronald F. DeMara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Scopus citations

Abstract

A low-energy hardware implementation of deep belief network (DBN) architecture is developed using near-zero energy barrier probabilistic spin logic devices (p-bits), which are modeled to realize an intrinsic sigmoidal activation function. A CMOS/spin based weighted array structure is designed to implement a restricted Boltzmann machine (RBM). Device-level simulations based on precise physics relations are used to validate the sigmoidal relation between the output probability of a p-bit and its input currents. Characteristics of the resistive networks and p-bits are modeled in SPICE to perform a circuit-level simulation investigating the performance, area, and power consumption tradeoffs of the weighted array. In the application-level simulation, a DBN is implemented in MATLAB for digit recognition using the extracted device and circuit behavioral models. The MNIST data set is used to assess the accuracy of the DBN using 5,000 training images for five distinct network topologies. The results indicate that a baseline error rate of 36.8% for a 784×10 DBN trained by 100 samples can be reduced to only 3.7% using a 784×800×800×10 DBN trained by 5,000 input samples. Finally, Power dissipation and accuracy tradeoffs for probabilistic computing mechanisms using resistive devices are identified.

Original languageEnglish (US)
Title of host publicationGLSVLSI 2018 - Proceedings of the 2018 Great Lakes Symposium on VLSI
PublisherAssociation for Computing Machinery
Pages15-20
Number of pages6
ISBN (Electronic)9781450357241
DOIs
StatePublished - May 30 2018
Event28th Great Lakes Symposium on VLSI, GLSVLSI 2018 - Chicago, United States
Duration: May 23 2018May 25 2018

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Other

Other28th Great Lakes Symposium on VLSI, GLSVLSI 2018
Country/TerritoryUnited States
CityChicago
Period5/23/185/25/18

Bibliographical note

Funding Information:
This work was supported in part by the Center for Probabilistic Spin Logic for Low-Energy Boolean and Non-Boolean Computing (CAPSL), one of the Nanoelectronic Computing Research (nCORE) Centers as task 2759.006, a Semiconductor Research Corporation (SRC) program sponsored by the NSF through CCF 1739635.

Publisher Copyright:
© 2018 Copyright held by the owner/author(s).

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