Low-latency architectures for high-throughput rate Viterbi decoders

Jun Jin Kong, Keshab K. Parhi

Research output: Contribution to journalArticlepeer-review

14 Scopus citations

Abstract

In this paper, a novel K-nested layered look-ahead method and its corresponding architecture, which combine K-trellis steps into one trellis step (where K is the encoder constraint length), are proposed for implementing low-latency high-throughput rate Viterbi decoders. The proposed method guarantees parallel paths between any two-trellis states in the look-ahead trellises and distributes the add-compare-select (ACS) computations to all trellis layers. It leads to regular and simple architecture for the Viterbi decoding algorithm. The look-ahead ACS computation latency of the proposed method increases logarithmically with respect to the look-ahead step (M) divided by the encoder constraint length (K) as opposed to linearly as in prior work. For a 4-state (i.e., K = 3) convolutional code, the decoding latency of the Viterbi decoder using proposed method is reduced by 84%, at the expense of about 22% increase in hardware complexity, compared with conventional M-step look-ahead method with M = 48 (where M is also the level of parallelism). The main advantage of our proposed design is that it has the least latency among all known look-ahead Viterbi decoders for a given level of parallelism.

Original languageEnglish (US)
Pages (from-to)642-651
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume12
Issue number6
DOIs
StatePublished - Jun 2004

Bibliographical note

Funding Information:
Manuscript received June 17, 2003; revised December 10, 2003. The work of J. J. Kong was supported by Samsung Advanced Institute of Technology, Suwon, Korea. This work was carried out at the University of Minnesota, Minneapolis.

Keywords

  • Add-compare-select (ACS)
  • High-throughput rate Viterbi decoder
  • Look-ahead method
  • Low-latency Viterbi decoder architecture

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