Low-power bit-serial viterbi decoder for 3rd generation W-CDMA systems

Hiroshi Suzuki, Yun Nan Chang, Keshab K. Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

This paper presents a low-power bit-serial Viterbi decoder chip with the coding rate r = 1/3 and the constraint length K = 9 (256 states). This chip is targeted for high speed convolutional decoding for next generation wireless applications. The Add-Compare-Select (ACS) units have been designed using bit-serial arithmetic and a power efficient trace-back scheme and an application-specific memory have been developed for the trace-back operation. The chip was implemented using 0.5μm CMOS technology and is operative at 20Mbps under 3.3V and at 2Mbps under 1.8V. The power dissipation is only 9.8mW at 2Mbps operation under 1.8V.

Original languageEnglish (US)
Title of host publicationProceedings of the Custom Integrated Circuits Conference
PublisherIEEE
Pages589-592
Number of pages4
ISBN (Print)0780354443
StatePublished - Jan 1 1999
EventProceedings of the 1999 21st IEEE Annual Custom Integrated Circuits Conference, CICC '99 - San Diego, CA, USA
Duration: May 16 1999May 19 1999

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Other

OtherProceedings of the 1999 21st IEEE Annual Custom Integrated Circuits Conference, CICC '99
CitySan Diego, CA, USA
Period5/16/995/19/99

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