@inproceedings{3e41219459ae421da342ab99ee375d25,
title = "Low-power bit-serial viterbi decoder for 3rd generation W-CDMA systems",
abstract = "This paper presents a low-power bit-serial Viterbi decoder chip with the coding rate r = 1/3 and the constraint length K = 9 (256 states). This chip is targeted for high speed convolutional decoding for next generation wireless applications. The Add-Compare-Select (ACS) units have been designed using bit-serial arithmetic and a power efficient trace-back scheme and an application-specific memory have been developed for the trace-back operation. The chip was implemented using 0.5μm CMOS technology and is operative at 20Mbps under 3.3V and at 2Mbps under 1.8V. The power dissipation is only 9.8mW at 2Mbps operation under 1.8V.",
author = "Hiroshi Suzuki and Chang, {Yun Nan} and Parhi, {Keshab K.}",
year = "1999",
month = jan,
day = "1",
language = "English (US)",
isbn = "0780354443",
series = "Proceedings of the Custom Integrated Circuits Conference",
publisher = "IEEE",
pages = "589--592",
booktitle = "Proceedings of the Custom Integrated Circuits Conference",
note = "Proceedings of the 1999 21st IEEE Annual Custom Integrated Circuits Conference, CICC '99 ; Conference date: 16-05-1999 Through 19-05-1999",
}