Supply voltage overscaling has been studied recently for the design of low power finite impulse response (FIR) filters, where the supply voltage is deliberately scaled beyond the critical voltage so as to lower the power consumption quadratically. The violation of timing constraint leads to computational errors/noise, which is then reduced via prediction-based algorithms. In this paper, we first propose an estimation-based algorithm aiming at accuracy maximization. Then, practical design issues are addressed and the major problem that causes performance drop is identified, which leads to a novel flexible twophase bilateral estimation-based noise reduction architecture with the use of error-delay detection mechanism that enables the flexible size estimator. Compared to conventional designs, simulation results show that the estimation-based algorithm and the two-phase bilateral estimation algorithm improve the noise reduction performance by 10-20dB and 17-22dB while achieving the same power saving ratio, respectively. Alternatively, the proposed algorithms can achieve lower power while a certain performance requirement is satisfied.