Memory module-level testing and error behaviors for phase change memory

Zhe Zhang; Weijun Xiao; Nohhyun Park; David J. Lilja

doi:10.1109/ICCD.2012.6378664

Memory module-level testing and error behaviors for phase change memory

Zhe Zhang, Weijun Xiao, Nohhyun Park, David J. Lilja

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

15 Scopus citations

Abstract

Phase change memory (PCM) is a promising technology to solve energy and performance bottlenecks for memory and storage systems. To help understand the reliability characteristics of PCM devices, we present a simple fault model to categorize four types of PCM errors. Based on our proposed fault model, we conduct extensive experiments on real PCM devices at the memory module level. Numerical results uncover many interesting trends in terms of the lifetime of PCM devices and error behaviors. Specifically, PCM lifetime for the memory chips we tested is greater than 14 million cycles, which is much longer than for flash memory devices. In addition, the distributions for four types of errors are quite different. These results can be used for estimating PCM lifetime and for measuring the fabrication quality of individual PCM memory chips.

Original language	English (US)
Title of host publication	2012 IEEE 30th International Conference on Computer Design, ICCD 2012
Pages	358-363
Number of pages	6
DOIs	https://doi.org/10.1109/ICCD.2012.6378664
State	Published - 2012
Event	2012 IEEE 30th International Conference on Computer Design, ICCD 2012 - Montreal, QC, Canada Duration: Sep 30 2012 → Oct 3 2012

Publication series

Name	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
ISSN (Print)	1063-6404

Other

Other	2012 IEEE 30th International Conference on Computer Design, ICCD 2012
Country/Territory	Canada
City	Montreal, QC
Period	9/30/12 → 10/3/12

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10.1109/ICCD.2012.6378664

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Zhang, Z., Xiao, W., Park, N., & Lilja, D. J. (2012). Memory module-level testing and error behaviors for phase change memory. In 2012 IEEE 30th International Conference on Computer Design, ICCD 2012 (pp. 358-363). Article 6378664 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors). https://doi.org/10.1109/ICCD.2012.6378664

Memory module-level testing and error behaviors for phase change memory. / Zhang, Zhe; Xiao, Weijun; Park, Nohhyun et al.
2012 IEEE 30th International Conference on Computer Design, ICCD 2012. 2012. p. 358-363 6378664 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Zhang, Z, Xiao, W, Park, N & Lilja, DJ 2012, Memory module-level testing and error behaviors for phase change memory. in 2012 IEEE 30th International Conference on Computer Design, ICCD 2012., 6378664, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 358-363, 2012 IEEE 30th International Conference on Computer Design, ICCD 2012, Montreal, QC, Canada, 9/30/12. https://doi.org/10.1109/ICCD.2012.6378664

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abstract = "Phase change memory (PCM) is a promising technology to solve energy and performance bottlenecks for memory and storage systems. To help understand the reliability characteristics of PCM devices, we present a simple fault model to categorize four types of PCM errors. Based on our proposed fault model, we conduct extensive experiments on real PCM devices at the memory module level. Numerical results uncover many interesting trends in terms of the lifetime of PCM devices and error behaviors. Specifically, PCM lifetime for the memory chips we tested is greater than 14 million cycles, which is much longer than for flash memory devices. In addition, the distributions for four types of errors are quite different. These results can be used for estimating PCM lifetime and for measuring the fabrication quality of individual PCM memory chips.",

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Memory module-level testing and error behaviors for phase change memory

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