TY - GEN
T1 - Minimal complexity low-latency architectures for Viterbi decoders
AU - Liu, Renfei
AU - Parhi, Keshab K.
PY - 2008
Y1 - 2008
N2 - For Viterbi decoders, high throughput rate is achieved by applying look-ahead techniques in the add-compare-select unit, which is the system speed bottleneck. Look-ahead techniques combine multiple binary trellis steps into one equivalent complex trellis step in time sequence, which is referred to as the branch metrics precomputation (BMP) unit. The complexity and latency of BMP increase exponentially and linearly with respect to the look-ahead levels, respectively. For a Viterbi decoder with constraint length K and M-step look-ahead, 2M+K-1 branch metrics need to be computed and compared. In this paper, the computational redundancy in existing branch metric computation approaches is first recognized, and a general mathematical model for describing the approach space is built, based on which a new approach with minimal complexity and latency is proposed. The proof of its optimality is also given. This highly efficient approach leads to a novel overall optimal architecture for M that is any multiple of K. The results show that the proposed approaches can reduce the complexity by up to 45.65% and the latency by up to 72.50%. In addition, the proposed architecture can also be applied when M is any value while achieving the minimal complexity.
AB - For Viterbi decoders, high throughput rate is achieved by applying look-ahead techniques in the add-compare-select unit, which is the system speed bottleneck. Look-ahead techniques combine multiple binary trellis steps into one equivalent complex trellis step in time sequence, which is referred to as the branch metrics precomputation (BMP) unit. The complexity and latency of BMP increase exponentially and linearly with respect to the look-ahead levels, respectively. For a Viterbi decoder with constraint length K and M-step look-ahead, 2M+K-1 branch metrics need to be computed and compared. In this paper, the computational redundancy in existing branch metric computation approaches is first recognized, and a general mathematical model for describing the approach space is built, based on which a new approach with minimal complexity and latency is proposed. The proof of its optimality is also given. This highly efficient approach leads to a novel overall optimal architecture for M that is any multiple of K. The results show that the proposed approaches can reduce the complexity by up to 45.65% and the latency by up to 72.50%. In addition, the proposed architecture can also be applied when M is any value while achieving the minimal complexity.
KW - Look-ahead technique
KW - Low complexity
KW - Low latency
KW - Pre-computation
KW - Trellis
KW - Viterbi decoder
UR - http://www.scopus.com/inward/record.url?scp=57849155813&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=57849155813&partnerID=8YFLogxK
U2 - 10.1109/SIPS.2008.4671752
DO - 10.1109/SIPS.2008.4671752
M3 - Conference contribution
AN - SCOPUS:57849155813
SN - 9781424429240
T3 - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
SP - 140
EP - 145
BT - 2008 IEEE Workshop on Signal Processing Systems, SiPS 2008, Proceedings
T2 - 2008 IEEE Workshop on Signal Processing Systems, SiPS 2008
Y2 - 8 October 2008 through 10 October 2008
ER -