Abstract
Directory-based cache coherence schemes are commonly used in large-scale shared-memory multiprocessors, but most of them rely on heuristics to avoid large hardware requirements. We proposed using physical address mapping on directories to significantly reduce directory size needed. This approach allows the size of directory to grow as O(cn log2 n) as in optimal pointer-based directory schemes [11], where n is the number of nodes in the system and c is the number of cache lines in each cache memory. Performance aspects of the proposed scheme are studied in detail using simulation.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 2533-2542 |
| Number of pages | 10 |
| Journal | IEICE Transactions on Information and Systems |
| Volume | E88-D |
| Issue number | 11 |
| DOIs | |
| State | Published - Nov 2005 |
Bibliographical note
Funding Information:Author's research was partially supported by PSC-CUNY and NSF grants. 06 2003 68 2 669 688 25 02 2002 02 01 2003 Copyright © Association for Symbolic Logic 2003 2003 Association for Symbolic Logic
Funding Information:
Both authors wish to thank the CUNY Research Foundation for the Collaborative Incentive Grant that partially supported their research.
Funding Information:
Author's research was partially supported by PSC-CUNY Grants 61449-00-30 and 63436-00-32.
Keywords
- Cache coherence
- Directory protocol
- Multiprocessor
- Shared memory architecture