MRAM DTCO and compact models

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Design-Technology Co-Optimization (DTCO) has become an important design methodology for making early decisions on technology, circuit, and system design parameters. This invited paper introduces various aspects of DTCO for MRAM development, ranging from SPICE compatible Magnetic Tunnel Junction (MTJ) device models, array level spin transfer torque magnetoresistive random access memory (STT-MRAM) power-performance-area (PPA) evaluation, scalability and variability studies of large-scale arrays, and novel read and write circuit techniques.

Original languageEnglish (US)
Title of host publication2020 IEEE International Electron Devices Meeting, IEDM 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages41.6.1-41.6.4
ISBN (Electronic)9781728188881
DOIs
StatePublished - Dec 12 2020
Event66th Annual IEEE International Electron Devices Meeting, IEDM 2020 - Virtual, San Francisco, United States
Duration: Dec 12 2020Dec 18 2020

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
Volume2020-December
ISSN (Print)0163-1918

Conference

Conference66th Annual IEEE International Electron Devices Meeting, IEDM 2020
CountryUnited States
CityVirtual, San Francisco
Period12/12/2012/18/20

Bibliographical note

Funding Information:
ACKNOWLEDGMENT This work was supported in part by C-SPIN, one of the six SRC STARnet Centers, through MARCO and DARPA and in part by the NSF/SRC E2CDA Program.

Publisher Copyright:
© 2020 IEEE.

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