TY - JOUR
T1 - Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources
AU - Selvakkumaran, Navaratnasothie
AU - Ranjan, Abhishek
AU - Raje, Salil
AU - Karypis, George
PY - 2004
Y1 - 2004
N2 - As FPGA densities increase, partitioning-based FPGA placement approaches are becoming increasingly important as they can be used to provide high-quality and computationally scalable placement solutions. However, modern FPGA architectures incorporate heterogeneous resources, which place additional requirements on the partitioning algorithms because they now need to not only minimize the cut and balance the partitions, but also they must ensure that none of the resources in each partition is oversubscribed. In this paper, we present a number of multilevel multi-resource hypergraph partitioning algorithms that are guaranteed to produce solutions that balance the utilization of the different resources across the partitions. We evaluate our algorithms on twelve industrial benchmarks ranging in size from 5,236 to 140, 118 vertices and show that they achieve minimal degradation in the min-cut while balancing the various resources. Comparing the quality of the solution produced by some of our algorithms against that produced by hMETlS, we show that our algorithms are capable of balancing the different resources while incurring only a 3.3%-5.7% higher cut.
AB - As FPGA densities increase, partitioning-based FPGA placement approaches are becoming increasingly important as they can be used to provide high-quality and computationally scalable placement solutions. However, modern FPGA architectures incorporate heterogeneous resources, which place additional requirements on the partitioning algorithms because they now need to not only minimize the cut and balance the partitions, but also they must ensure that none of the resources in each partition is oversubscribed. In this paper, we present a number of multilevel multi-resource hypergraph partitioning algorithms that are guaranteed to produce solutions that balance the utilization of the different resources across the partitions. We evaluate our algorithms on twelve industrial benchmarks ranging in size from 5,236 to 140, 118 vertices and show that they achieve minimal degradation in the min-cut while balancing the various resources. Comparing the quality of the solution produced by some of our algorithms against that produced by hMETlS, we show that our algorithms are capable of balancing the different resources while incurring only a 3.3%-5.7% higher cut.
KW - FPGA
KW - Hierarchical
KW - Multi-constraint
KW - Multi-resource
KW - Partitioning
KW - Placement
UR - http://www.scopus.com/inward/record.url?scp=4444239804&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=4444239804&partnerID=8YFLogxK
U2 - 10.1145/996566.996768
DO - 10.1145/996566.996768
M3 - Conference article
AN - SCOPUS:4444239804
SN - 0738-100X
SP - 741
EP - 746
JO - Proceedings - Design Automation Conference
JF - Proceedings - Design Automation Conference
T2 - Proceedings of the 41st Design Automation Conference
Y2 - 7 June 2004 through 11 June 2004
ER -