@inproceedings{9dbd0e665f324889805dcd21cca8fb90,
title = "MULTIPROCESSOR CACHE DESIGN CONSIDERATIONS.",
abstract = "Cache design is explored for large high-performance multiprocessors with hundreds or thousands of processors and memory modules interconnected by a pipelined multistage network. Multiprocessor conditions are identified and modeled, including: (1) the cost of a cache coherence enforcement scheme; (2) the effect of a high degree of overlap between cache miss services; (3) the cost of a pin-limited data path between shared memory and caches; (4) the effect of a high degree of data prefetching; (5) the program behavior of a scientific workload, as represented by 23 numerical subroutines; and (6) the parallel execution of programs. This model is used to show that the cache miss ratio is not a suitable performance measure in the multiprocessors of interest and to show that the optimal cache block size in such multiprocessors is much smaller than in many uniprocessors.",
author = "Lee, {Roland L.} and Yew, {Pen Chung} and Lawrie, {Duncan H.}",
year = "1987",
doi = "10.1145/30350.30379",
language = "English (US)",
isbn = "0818607769",
series = "Conference Proceedings - Annual Symposium on Computer Architecture",
publisher = "IEEE",
pages = "253--262",
booktitle = "Conference Proceedings - Annual Symposium on Computer Architecture",
}