Network-on-Chip for Turbo Decoders

Qingqing Yang; Xiaofang Zhou; Gerald Edward Sobelman; Xinxin Li

doi:10.1109/TVLSI.2015.2390264

Network-on-Chip for Turbo Decoders

Qingqing Yang, Xiaofang Zhou, Gerald Edward Sobelman, Xinxin Li

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

3 Scopus citations

Abstract

The multi-application specific instruction processor (ASIP) architecture is a promising candidate for flexible high-throughput turbo decoders. This brief proposes a network-on-chip (NoC) structure for multi-ASIP turbo decoders. The process of turbo decoding is studied, and the addressing patterns for turbo codes in long term evolution (LTE) and High Speed Downlink Packet Access (HSDPA) are analyzed. Based on this analysis, two techniques, subnetworking and calculation sequence, are proposed for reducing the complexity of the NoC. The implementation results show that the proposed structure gives an improvement of 53% for HSDPA and 133% for LTE in throughput/area efficiency compared with state-of-the-art NoC solutions.

Original language	English (US)
Article number	7035055
Pages (from-to)	338-342
Number of pages	5
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	24
Issue number	1
DOIs	https://doi.org/10.1109/TVLSI.2015.2390264
State	Published - Jan 2016

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Keywords

Network-on-chip (NoC)
VLSI
turbo decoder

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abstract = "The multi-application specific instruction processor (ASIP) architecture is a promising candidate for flexible high-throughput turbo decoders. This brief proposes a network-on-chip (NoC) structure for multi-ASIP turbo decoders. The process of turbo decoding is studied, and the addressing patterns for turbo codes in long term evolution (LTE) and High Speed Downlink Packet Access (HSDPA) are analyzed. Based on this analysis, two techniques, subnetworking and calculation sequence, are proposed for reducing the complexity of the NoC. The implementation results show that the proposed structure gives an improvement of 53% for HSDPA and 133% for LTE in throughput/area efficiency compared with state-of-the-art NoC solutions.",

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Network-on-Chip for Turbo Decoders

Abstract

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Keywords

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