Network-on-chip link analysis under power and performance constraints

Manho Kim, Daewook Kim, Gerald E. Sobelman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Scopus citations

Abstract

This paper analyzes the behavior of interconnects in the highly structured environment of a network-on-chip (NoC). Two distinct classes of wires are considered, namely links between adjacent routers and links between a router and an attached processing element (PE). Analytical models for global router-to-router links and semi-global router-to-PE links are studied. Power and performance optimizations are obtained for each of these two classes of interconnections.

Original languageEnglish (US)
Title of host publicationISCAS 2006
Subtitle of host publication2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages4163-4166
Number of pages4
StatePublished - 2006
EventISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece
Duration: May 21 2006May 24 2006

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

OtherISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
CountryGreece
CityKos
Period5/21/065/24/06

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