New architecture of low voltage sigma-delta ADC

Jiaxin Ju, Wanrong Zhang, Haolin Du, Yanfeng Jiang, Yamin Zhang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations


A low voltage low power sigma delta modulator was presented. A sigma delta modulator architecture which was very adapt to low voltage low power applications was proposed. With the advantage of both unity gain sigma delta modulator and traditional sigma delta modulator, it relaxed the requirement of the OTA performance and decreased the complex of the circuit. For lower power consumption as soon as possible, the technique of negative resistance load was used to improve the dc gain of the current mirror OTA and the technique of Class-AB output stage was used for lower power consumption. Simulation results showed that with 0.18um CMOS technology, 20 KHz signal bandwidth and oversampling rate of 156, the modulator achieved 93dB dynamic range, the power consumption was 500uW under 1V supply voltage and the chip core size was 0.5mm2. Measure results showed that with 2MHz sampling frequency and 1KHz input signal the sigma delta modulator achieved 65dB SNR and 60dB SNDR.

Original languageEnglish (US)
Title of host publicationASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC
Number of pages4
StatePublished - Dec 1 2009
Event2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha, China
Duration: Oct 20 2009Oct 23 2009

Publication series

NameASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC


Other2009 8th IEEE International Conference on ASIC, ASICON 2009


  • Current mirror OTA
  • Low voltage low power consumption
  • Switched capacitor sigma delta modulator


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