TY - GEN
T1 - Notice of Removal
T2 - 2009 8th IEEE International Conference on ASIC, ASICON 2009
AU - Ju, Jiaxin
AU - Zhang, Wanrong
AU - Du, Haolin
AU - Jiang, Yanfeng
AU - Zhang, Yamin
PY - 2009
Y1 - 2009
N2 - A low voltage low power sigma delta modulator was presented. A sigma delta modulator architecture which was very adapt to low voltage low power applications was proposed. With the advantage of both unity gain sigma delta modulator and traditional sigma delta modulator, it relaxed the requirement of the OTA performance and decreased the complex of the circuit. For lower power consumption as soon as possible, the technique of negative resistance load was used to improve the dc gain of the current mirror OTA and the technique of Class-AB output stage was used for lower power consumption. Simulation results showed that with 0.18um CMOS technology, 20 KHz signal bandwidth and oversampling rate of 156, the modulator achieved 93dB dynamic range, the power consumption was 500uW under 1V supply voltage and the chip core size was 0.5mm2. Measure results showed that with 2MHz sampling frequency and 1KHz input signal the sigma delta modulator achieved 65dB SNR and 60dB SNDR.
AB - A low voltage low power sigma delta modulator was presented. A sigma delta modulator architecture which was very adapt to low voltage low power applications was proposed. With the advantage of both unity gain sigma delta modulator and traditional sigma delta modulator, it relaxed the requirement of the OTA performance and decreased the complex of the circuit. For lower power consumption as soon as possible, the technique of negative resistance load was used to improve the dc gain of the current mirror OTA and the technique of Class-AB output stage was used for lower power consumption. Simulation results showed that with 0.18um CMOS technology, 20 KHz signal bandwidth and oversampling rate of 156, the modulator achieved 93dB dynamic range, the power consumption was 500uW under 1V supply voltage and the chip core size was 0.5mm2. Measure results showed that with 2MHz sampling frequency and 1KHz input signal the sigma delta modulator achieved 65dB SNR and 60dB SNDR.
KW - Current mirror OTA
KW - Low voltage low power consumption
KW - Switched capacitor sigma delta modulator
UR - http://www.scopus.com/inward/record.url?scp=77949385471&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77949385471&partnerID=8YFLogxK
U2 - 10.1109/ASICON.2009.5351497
DO - 10.1109/ASICON.2009.5351497
M3 - Conference contribution
AN - SCOPUS:77949385471
SN - 9781424438686
T3 - ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC
SP - 203
EP - 206
BT - ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC
PB - IEEE Computer Society
Y2 - 20 October 2009 through 23 October 2009
ER -