NIUGAP: Low latency network interface architecture with gray code for networks-on-chip

Kim Daewook, Kim Manho, Gerald E Sobelman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

The implementation of a high-performance network-on-chip (NoC) requires an efficient design for the network interface unit (NIU) that connects the switched network to the IP cores. In this paper, we present a novel NIU architecture that utilizes a Gray code based packet reordering methodology to achieve low latency packet processing. The proposed architecture has been implemented with VHDL and synthesized using a 0.25 μm ASIC technology. Simulation results verify the functionality of the architecture and show that it can save a substantial amount of packet processing time compared to the conventional reordering scheme.

Original languageEnglish (US)
Title of host publicationISCAS 2006
Subtitle of host publication2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages3902-3905
Number of pages4
StatePublished - Dec 1 2006
EventISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece
Duration: May 21 2006May 24 2006

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

OtherISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Country/TerritoryGreece
CityKos
Period5/21/065/24/06

Fingerprint

Dive into the research topics of 'NIUGAP: Low latency network interface architecture with gray code for networks-on-chip'. Together they form a unique fingerprint.

Cite this