A hierarchically structured framework for analog circuit synthesis is described. Analog circuit topologies are represented as a hierarchy of templates of abstract functional blocks (called design styles) each with associated detailed design knowledge. This hierarchical structure has two important features: it decomposes the design task into a sequence of smaller tasks with uniform structure, and it simplifies the reuse of design knowledge. Mechanisms are described to select from among alternate design styles, and to translate performance specifications from one level in the hierarchy to the next lower, more concrete level. A prototype implementation, OASYS, synthesizes sized transistor schematics for CMOS operational amplifiers from performance specifications and process parameters. Measurements from detailed circuit simulation, and from actual fabricated analog IC-s based on OASYS-synthesized designs demonstrate that OASYS is capable of synthesizing functional circuits.
|Original language||English (US)|
|Number of pages||20|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|State||Published - Dec 1989|
Bibliographical noteFunding Information:
Manuscript received March 21, 1988; revised February 10, 1989 and June 21, 1989. This work was supported in part by the Semiconductor Research Corporation, by a grant from the Gould Foundation, and by the National Science Foundation under Grants ENG-845 1496 and MIP-8657369. This paper was recommended by Associate Editor M. R. Light-ner. R. Harjani was with the Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA. He is now with Mentor Graphics, San Jose, CA 95112. R. A. Rutenbar and L. R. Carley are with the Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213. IEEE Log Number 8930646.