On-Chip Neural Data Compression Based on Compressed Sensing with Sparse Sensing Matrices

Wenfeng Zhao, Biao Sun, Tong Wu, Zhi Yang

Research output: Contribution to journalArticlepeer-review

11 Scopus citations


On-chip neural data compression is an enabling technique for wireless neural interfaces that suffer from insufficient bandwidth and power budgets to transmit the raw data. The data compression algorithm and its implementation should be power and area efficient and functionally reliable over different datasets. Compressed sensing is an emerging technique that has been applied to compress various neurophysiological data. However, the state-of-the-art compressed sensing (CS) encoders leverage random but dense binary measurement matrices, which incur substantial implementation costs on both power and area that could offset the benefits from the reduced wireless data rate. In this paper, we propose two CS encoder designs based on sparse measurement matrices that could lead to efficient hardware implementation. Specifically, two different approaches for the construction of sparse measurement matrices, i.e., the deterministic quasi-cyclic array code (QCAC) matrix and $(1,s)$-sparse random binary matrix [(1,s) -SRBM] are exploited. We demonstrate that the proposed CS encoders lead to comparable recovery performance. And efficient VLSI architecture designs are proposed for QCAC-CS and (1,s)-SRBM encoders with reduced area and total power consumption.

Original languageEnglish (US)
Article number8253901
Pages (from-to)242-254
Number of pages13
JournalIEEE transactions on biomedical circuits and systems
Issue number1
StatePublished - Feb 2018


  • Compressed sensing
  • EEG
  • VLSI
  • data compression
  • sparse sensing matrix
  • spike sorting
  • wireless neural interface

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