Front-end-of-line reliability issues such as Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), and Time Dependent Dielectric Breakdown (TDDB) have become more prevalent as electrical fields continue to increase in scaled devices. The rapid introduction of process improvements, such as high-k/metal gate stacks and strained silicon, has lead to new reliability issues including BTI in n-type devices. Precise measurements of the circuit degradation induced by these reliability mechanisms are a key aspect of robust design. This article will review a number of unique test chip designs pursued by circuit designers that demonstrate the benefits of utilizing on-chip logic and a simple test interface to automate circuit aging experiments. This new class of compact on-chip sensors can reveal important aspects of circuit aging that would otherwise be impossible to measure, and can lead us down the path to real-time aging compensation in future processors.
Bibliographical noteFunding Information:
This work was supported in part by the Semiconductor Research Corporation (SRC) under award 2008-HJ-1805, and an IBM Ph.D. fellowship award. The authors would also like to thank Intel, IBM, Broadcom, AMD, Freescale, Texas Instruments, and Samsung for the technical feedback and financial support.