Abstract
Recently a novel algorithm transformation was proposed to reduce the critical path of Berlekamp-Massey algorithm implementation for errors-alone Reed-Solomon decoding. In this paper, we apply the same methodology to transform the Berlekamp-Massey algorithm for errors-and-erasures RS decoding. We present a regular hardware architecture to implement the reformulated Berlekamp-Massey algorithm, which can achieve high throughput. Moreover, an operation scheduling scheme is proposed to further reduce the hardware complexity without loss of throughput.
Original language | English (US) |
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Title of host publication | GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI |
Publisher | Association for Computing Machinery, Inc |
Pages | 89-93 |
Number of pages | 5 |
ISBN (Electronic) | 1581134622, 9781581134629 |
DOIs | |
State | Published - Apr 18 2002 |
Event | 12th ACM Great Lakes Symposium on VLSI, GLSVLSI 2002 - New York, United States Duration: Apr 18 2002 → Apr 19 2002 |
Publication series
Name | GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI |
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Other
Other | 12th ACM Great Lakes Symposium on VLSI, GLSVLSI 2002 |
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Country/Territory | United States |
City | New York |
Period | 4/18/02 → 4/19/02 |
Bibliographical note
Publisher Copyright:Copyright 2002 ACM.
Keywords
- Berlekamp-massey algorithm
- Erasure
- Reed-solomon codes
- VLSI architectures