On the high-speed VLSI implementation of errors-and-erasures correcting Reed-Solomon decoders

Tong Zhang, Keshab K. Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

Recently a novel algorithm transformation was proposed to reduce the critical path of Berlekamp-Massey algorithm implementation for errors-alone Reed-Solomon decoding. In this paper, we apply the same methodology to transform the Berlekamp-Massey algorithm for errors-and-erasures RS decoding. We present a regular hardware architecture to implement the reformulated Berlekamp-Massey algorithm, which can achieve high throughput. Moreover, an operation scheduling scheme is proposed to further reduce the hardware complexity without loss of throughput.

Original languageEnglish (US)
Title of host publicationGLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI
PublisherAssociation for Computing Machinery, Inc
Pages89-93
Number of pages5
ISBN (Electronic)1581134622, 9781581134629
DOIs
StatePublished - Apr 18 2002
Event12th ACM Great Lakes Symposium on VLSI, GLSVLSI 2002 - New York, United States
Duration: Apr 18 2002Apr 19 2002

Publication series

NameGLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI

Other

Other12th ACM Great Lakes Symposium on VLSI, GLSVLSI 2002
CountryUnited States
CityNew York
Period4/18/024/19/02

Keywords

  • Berlekamp-massey algorithm
  • Erasure
  • Reed-solomon codes
  • VLSI architectures

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