Abstract
In this paper we consider the problem of determining a valid clock setting for a combinational circuit. The performance of a circuit depends on its clock period. The shorter a valid clock period is, the better the performance is. We have proposed two new bounds for clock period by considering a type of paths called functionally sensitizable paths. Then these results are extended to wavepipelined circuits. We have compared the new bounds with the previously proposed bounds and it has been shown that these new bounds may have better performance for certain combinational circuits. We have also given an example to show that the path delays obtained by two-vector model may not be valid when used for clock setting. The bounds on clock period can alternatively be viewed as optimization objectives. We present some experimental results to show various bounds on clock period for ISCAS benchmark circuits and discuss the potential complexity of optimizing circuits with these bounds.
| Original language | English (US) |
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| Pages | 381-384 |
| Number of pages | 4 |
| State | Published - 1994 |
| Event | Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors - Cambridge, MA, USA Duration: Oct 10 1994 → Oct 12 1994 |
Other
| Other | Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors |
|---|---|
| City | Cambridge, MA, USA |
| Period | 10/10/94 → 10/12/94 |